COMPUTER ORGANIZATION AND ARCHITECTURE
(CPU Control Design, Memory Interface, I/O Interface)
Practice SET 4
1. Consider a logical address space of 8 pages of 512 words each mapped onto a physical memory of 64 frames. How many bits are there in physical address?
2. How many cycles are required for a 100 MHz processor to execute a program which requires 5 seconds of CPU time?
(a) 109 cycles (b) 50 × 107 cycles
(c) 108 cycles (d) 50 cycles
3. Arrange the following configurations for CPU in decreasing order of operating speeds.
1. Hard wired control
2. Vertical microprogramming
3. Horizontal microprogramming
(a) 1 > 2 > 3 (b) 1 > 3 > 2
(c) 2 > 3 > 1 (d) 3 > 2 > 1
4. A = 1111 1010, B = 0000 1010 be two 8-bit 2’s complement numbers. Their product in 2’s complement is
(a) 1100 0100 (b) 1001 1100
(c) 1010 0101 (d) 1101 0101
5. Main difference between CISC and RISC is
(a) RISC has few instructions (b) RISC has few addressing modes
(c) CISC is having fewer registers (d) Both (a) & (b)
6. A computer supports one address and two address instructions. All the Addresses are the memory addresses. Memory size is 1Mbyte. How many one address instructions are possible if it has 240 two addresses instructions? (Assume binary instructions code has 48 bits)
(a) 22016 (b) 16×220
(c) 228−256 (d) None of these
7. An interrupt program takes one cycle for every instruction. A DMA takes 15 cycles for initialization and 2 cycles for each Byte to transfer; what is the speed up of DMA over interrupt program of 5 instructions for the transfer of 100 Bytes? (Interrupt program must be executed for every byte)
8. How many separate address and data lines are needed for a memory of 8K × 16?
(a) 13 address, 3 data lines (b) 13 address, 16 data lines
(c) 12 address, 4 data lines (d) 13 address, 4 data lines
9. A system supports 1-address and 2-address instructions. If the instruction length is 16-bits and memory is having 64 words, how many 1-address instructions exists if there are ‘8’ 2-address instructions?
10. What is the average memory access time for a 3 level memory system where T2 = 2T1 and T3 = 3T1 and hit ratios h1 = h2 = 0.9. [Ti is effective access time]
(a) 1.11T1 (b) 1.22T1
(c) 1.09T1 (d) 1.01T1